Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Silicon Labs/Series1/EFM32GG11B/EFM32GG11B510F2048GL120/CMU/LFCCLKEN0#0x0
Low Frequency C Clock Enable Register 0 (Async Reg)
https://github.com/cmsis-svd/cmsis-svd-data